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verilog: Definition and Recommended Links

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Verilog is a hardware description language (HDL) used to model electronic systems. The language (sometimes called Verilog HDL) supports the design, verification, and implementation of analog, digital, and mixed-signal circuits at various levels of abstraction.

The designers of Verilog wanted a language with syntax similar to the C programming language so that it would be familiar to engineers and readily accepted. The language is case-sensitive, has a preprocessor like C, and the major control flow keywords, such as 'if' and 'while', are similar. The formatting mechanism in the printing routines and language operators and their precedence are also similar.

The language differs in some fundamental ways. Verilog uses Begin/End instead of curly braces to define a block of code. The definition of constants in Verilog require a bit width along with their base, consequently these differ. Verilog 95 and 2001 don't have structures, pointers, or recursive subroutines, however SystemVerilog now includes these capabilities. Finally, the concept of time —so important to a HDL— won't be found in C.

Source: Wikipedia (http://en.wikipedia.org/wiki/Verilog)

other great electronics sites:ee toolbox site

• • verilog
    • Verilog is a hardware description language (HDL) used to model electronic systems. The language (sometimes called Verilog HDL) supports the design, verification, and implementation of analog, digital, and mixed-signal circuits at various levels of abstraction.

      The designers of Verilog wanted a language with syntax similar to the C programming language so that it would be familiar to engineers and readily accepted. The language is case-sensitive, has a preprocessor like C, and the major control flow keywords, such as 'if' and 'while', are similar. The formatting mechanism in the printing routines and language operators and their precedence are also similar.

      The language differs in some fundamental ways. Verilog uses Begin/End instead of curly braces to define a block of code. The definition of constants in Verilog require a bit width along with their base, consequently these differ. Verilog 95 and 2001 don't have structures, pointers, or recursive subroutines, however SystemVerilog now includes these capabilities. Finally, the concept of time —so important to a HDL— won't be found in C.

      Source: Wikipedia (http://en.wikipedia.org/wiki/Verilog)

      (Note: The Electronic Engineers Toolbox provides an alternative set of featured links for this word at http://www.cera2.com/verilog.htm)

      Featured Links:

      Need help designing that high-speed serial design?

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      http://ad.doubleclick.net

      SystemVerilog

      Recently ratified hardware description and verification language (HDVL) standard – is a major extension of the established IEEE 1364-2001 Verilog language, and was developed by Accellera to dramatically improve productivity in the design of large gate count, IP-based, bus-intensive chips. SystemVerilog is targeted primarily at the chip implementation and verification flow, with powerful links to the system level design flow
      http://www.systemverilog.org/

      SystemVerilog @ Wikipedia

      SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog. SystemVerilog was created by the donation of the Superlog language to Accellera in 2002.[1] The bulk of the verification functionality is based on the OpenVera language donated by Synopsys. In 2005, SystemVerilog was adopted as IEEE Standard 1800-2005 .[1] Few of Systemverilog's capabilities are unique, but it is...
      http://en.wikipedia.org/wiki/Systemverilog

      Testbench.in - ASIC Functional Verification Tutorial

      There are many sources available for basic VLSI/DIGITAL and Hardware Description Languages(HDL's). As the Verification becomes the more and more complex and important there is a need of Hardware Verification Languages (HVL's) like Systemverilog, OpenVera... etc and Methodologies. But there isn't any great source available for Hardware Verification Languages(HVL's) and Methodologies. What's on this site : We believe the best and easiest...
      http://www.testbench.in/

      AlternateVerilog FAQ

      Alternate Verilog FAQ is an attempt to gather the answers to most Frequently Asked Questions about Verilog HDL in one place. It also contains list of publications, services, and products. Alternate Verilog FAQ is divided into three logical parts. Part 1 : Introduction and misc. questions Part 2 : Technical Topics Part 3 : Tools and Services
      http://www.angelfire.com/in/verilogfaq/

      EDA Industry Working Groups

      The Electronic Design Automation (EDA) and Electronic Computer-Aided Design (ECAD) one-stop standards resource. SystemVerilog : 3.0 LRM 3.1 LRM Basic and Design Committee Testbench and Enhancements C Interface Assertion. VHDL links
      http://www.eda.org/

      Aldec Releases Riviera-PRO 2008.06 HDL Simulator. Including New Assertions Waveform Viewer...

      Aldec, Inc., announced the release of Riviera-PRO 2008.06, a behavioral, structural and mixed HDL language simulator for multi-million gate ASIC and FPGA designs. Riviera-PRO 2008.06 includes Verilog® simulation performance enhancements, increased SystemVerilog support, seamless SystemC/C/C++ and HDL co-debugging in common environment and new support for SVA and PSL assertions in the Waveform Viewer. Riviera-PRO supports System Level...
      http://www.aldec.com

      FPGA Insiders' Guide

      Interested in FPGAs? FPGA makers like Xilinx or Altera, as well as board level providers and tools companies. FPGAs can be heaven or hell. This Insiders' Guide overviews the FPGA ecosystem, has survey results from real users, and interviews with leading vendors to help you figure out how to use FPGAs, boards, or tools to get your design done.
      http://www.fpga-report.org/

      Verilog Resources

      This web site is dedicated to Verilog in particular, and to Verifying Logic in general. To that end a collection of resources are available here; including an free editing mode for the verilog language; links to various books that are useful in understanding verilog, and verification in general; and links to same development tools.
      http://www.verilog.com/

      Eclipse Verilog editor

      Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.
      http://sourceforge.net/projects/veditor/

      Explanation: these links are provided as part of our EE glossary project, which seeks to identify the most prominent keywords in embedded systems, embedded software, realtime and rtos, dsp (digital signal processing), system-on-a-chip, microprocessors and microcontrollers, and other constituent elements for embedded systems. While we seek to keep most of the links up-to-date, the user is refered to other primary electronic-based search sites such as: cera2.com, embedded.com, or EDN Magazine. If you have any suggestions of links or definitions, please email!

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