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design for test: Definition and Recommended Links

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Design for Test (aka 'Design for Testability' or 'DFT') is a name for design techniques that add certain testability features to a microelectronic hardware product design. The premise of the added features is that they make it easier to develop and apply manufacturing tests for the designed hardware. The purpose of manufacturing tests is to validate that the product hardware contains no defects that could, otherwise, adversely affect the product’s correct functioning.

Tests are applied at several steps in the hardware manufacturing flow and, for certain products, may also be used for hardware maintenance in the customer’s environment. The tests generally are driven by test programs that execute in Automatic Test Equipment (ATE) or, in the case of system maintenance, inside the assembled system itself. In addition to finding and indicating the presence of defects (i.e., the test fails), tests may be able to log diagnostic information about the nature of the encountered test fails. The diagnostic information can be used to locate the source of the failure.

DFT plays an important role in the development of test programs and as an interface for test application and diagnostics. Automatic test pattern generation, or ATPG, is much easier if appropriate DFT rules and suggestions have been implemented.

Source: Wikipedia (http://en.wikipedia.org/wiki/Design_for_test)

other great electronics sites:ee toolbox site

• • design for test
    • Design for Test (aka 'Design for Testability' or 'DFT') is a name for design techniques that add certain testability features to a microelectronic hardware product design. The premise of the added features is that they make it easier to develop and apply manufacturing tests for the designed hardware. The purpose of manufacturing tests is to validate that the product hardware contains no defects that could, otherwise, adversely affect the product’s correct functioning.

      Tests are applied at several steps in the hardware manufacturing flow and, for certain products, may also be used for hardware maintenance in the customer’s environment. The tests generally are driven by test programs that execute in Automatic Test Equipment (ATE) or, in the case of system maintenance, inside the assembled system itself. In addition to finding and indicating the presence of defects (i.e., the test fails), tests may be able to log diagnostic information about the nature of the encountered test fails. The diagnostic information can be used to locate the source of the failure.

      DFT plays an important role in the development of test programs and as an interface for test application and diagnostics. Automatic test pattern generation, or ATPG, is much easier if appropriate DFT rules and suggestions have been implemented.

      Source: Wikipedia (http://en.wikipedia.org/wiki/Design_for_test)

      (Note: The Electronic Engineers Toolbox provides an alternative set of featured links for this word at http://www.cera2.com/design-for-test.htm)

      Featured Links:

      JTAG Free Resources

      We encourage you to take advantage of the following information on JTAG, available at no charge. View our Technical Leadership Video Access a FREE online Boundary-Scan (JTAG) Tutorial Access the first JTAG Tutorial (145-pages) written by ASSET InterTech when we were still at Texas Instruments. This primer explains the basics of JTAG, the benefits of JTAG testability, JTAG or boundary-scan architecture, some data formats and test flow....
      http://www.asset-intertech.com/products/free_resources.htm

      Built-in self-test (BIST) @ Wikipedia

      A built-in self-test (BIST) mechanism within an integrated circuit (IC) is a function that verifies all or a portion of the internal functionality of the IC. For example, a BIST mechanism is provided in advanced fieldbus systems to verify functionality. At a high level this can be viewed similar to the PC BIOS's Power-On Self-Test (POST) that performs a self-test of the RAM and buses on power-up.Alternative definition can be Built-in Self...
      http://en.wikipedia.org/wiki/BIST

      Mentor Graphics EDA Training and Employment Resources for Unemployed Designers

      Recently unemployed? Concerned about your EDA technical training? Christine Egli and Tom Floodeen of Mentor Graphics discuss how the company is reaching out to the EDA community to offer technical training in EDA (Electronic Design Automation) to 'displaced workers.' For those who qualify, the program is an excellent way to beef up your technical skills as well as to network with other EDA professionals seeking employment opportunities.
      http://www.eg3.com/etc-awards/20090324-mentor.htm

      Microprocessor Test and Verification (MTV'09)

      The purpose of MTV'09 is to bring together researchers and practitioners from all areas of work related to verification and test in order to exchange innovative ideas and present new methodologies for solving the challenges facing us today in various processor and SOC design environments. The workshop will take place in Austin, Texas, the live music capital of the world. Areas of Interest Validation of microprocessors and SOCs...
      http://mtv.ece.ucsb.edu/MTV/

      Tessent

      The Mentor Graphics Tessent™ product suite provides comprehensive silicon test and yield analysis solutions that address the challenges of manufacturing test, debug, and yield ramp for today’s SoCs. Built on the foundation of the best-in-class solutions for each test discipline, Tessent brings them together in a powerful test flow that ensures total chip coverage.
      http://www.mentor.com

      International Test Conference

      The world's premier conference dedicated to electronic test technology, covering the complete cycle from design verification, test, diagnosis, failure analysis back to process and design improvement.
      http://www.itctestweek.org/

      Calibre nmOPC

      The Calibre nmOPC tool offers best-in-class accuracy, speed, and cost of ownership. Like all Calibre family products, Calibre nmOPC runs on the fully integrated Calibre hierarchical geometry engine uniquely enabling a fully integrated design to mask flow with a unified command language. Calibre nmOPC also supports the OASIS output format to minimize output file size. Streamlined hierarchical processing algorithm in Calibre nmOPC enables the tool to take advantage of natural design hierarchy to improve turn around time, computational efficiency, and throughput compared to flat processing tools.
      http://www.mentor.com

      DFT Digest.com

      Hi! My name is John Ford, and I write this blog. I have been working in this industry for a little over 23 years (gasp!) in various engineering capacities: test (digital and mixed-signal), DFT, verification, and some design automation. I like doing a variety of things. The bulk of my career has been in Southern California, for companies such as Western Digital, Silicon Systems, and Texas Instruments. Just recently I worked for...
      http://www.dftdigest.com/

      Calibre nmDRC

      Total cycle time is on the rise due to more complex and larger designs, higher error counts and more verification iterations. Calibre® nmDRC responds to the need for reduced cycle time with revolutionary new capabilities that differentiate Calibre nmDRC substantially from traditional DRC tools including dynamic results visualization, equation-based DRC, direct database access and integrated DFM analysis.
      http://www.mentor.com

      Design of Systems on a Chip: Design and Test

      Second of two volumes addressing the design challenges associated with new generations of the semiconductor technology. The various chapters are the compilations of tutorials presented at workshops in the recent years by prominent authors from all over the world. Technology, productivity and quality are the main aspects under consideration to establish the major requirements for the design and test of upcoming systems on a chip. In...
      http://www.amazon.com

      Explanation: these links are provided as part of our EE glossary project, which seeks to identify the most prominent keywords in embedded systems, embedded software, realtime and rtos, dsp (digital signal processing), system-on-a-chip, microprocessors and microcontrollers, and other constituent elements for embedded systems. While we seek to keep most of the links up-to-date, the user is refered to other primary electronic-based search sites such as: cera2.com, embedded.com, or EDN Magazine. If you have any suggestions of links or definitions, please email!

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