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design for test: Definition and Recommended Links

Our favorite links for this topic area. Enjoy, fellow researchers! Questions, comments, new links? Email eewindow@aol.com!.

Design for Test (aka 'Design for Testability' or 'DFT') is a name for design techniques that add certain testability features to a microelectronic hardware product design. The premise of the added features is that they make it easier to develop and apply manufacturing tests for the designed hardware. The purpose of manufacturing tests is to validate that the product hardware contains no defects that could, otherwise, adversely affect the product’s correct functioning.

Tests are applied at several steps in the hardware manufacturing flow and, for certain products, may also be used for hardware maintenance in the customer’s environment. The tests generally are driven by test programs that execute in Automatic Test Equipment (ATE) or, in the case of system maintenance, inside the assembled system itself. In addition to finding and indicating the presence of defects (i.e., the test fails), tests may be able to log diagnostic information about the nature of the encountered test fails. The diagnostic information can be used to locate the source of the failure.

DFT plays an important role in the development of test programs and as an interface for test application and diagnostics. Automatic test pattern generation, or ATPG, is much easier if appropriate DFT rules and suggestions have been implemented.

Source: Wikipedia (http://en.wikipedia.org/wiki/Design_for_test)

other great electronics sites:ee toolbox site

• • design for test
    • Design for Test (aka 'Design for Testability' or 'DFT') is a name for design techniques that add certain testability features to a microelectronic hardware product design. The premise of the added features is that they make it easier to develop and apply manufacturing tests for the designed hardware. The purpose of manufacturing tests is to validate that the product hardware contains no defects that could, otherwise, adversely affect the product’s correct functioning.

      Tests are applied at several steps in the hardware manufacturing flow and, for certain products, may also be used for hardware maintenance in the customer’s environment. The tests generally are driven by test programs that execute in Automatic Test Equipment (ATE) or, in the case of system maintenance, inside the assembled system itself. In addition to finding and indicating the presence of defects (i.e., the test fails), tests may be able to log diagnostic information about the nature of the encountered test fails. The diagnostic information can be used to locate the source of the failure.

      DFT plays an important role in the development of test programs and as an interface for test application and diagnostics. Automatic test pattern generation, or ATPG, is much easier if appropriate DFT rules and suggestions have been implemented.

      Source: Wikipedia (http://en.wikipedia.org/wiki/Design_for_test)

      (Note: The Electronic Engineers Toolbox provides an alternative set of featured links for this word at http://www.cera2.com/design-for-test.htm)

      Featured Links:

      Design-for-Debug Consortium

      The DFD Consortium brings together electronic design automation (EDA), automated board test (ATE), and design for test (DFT) providers with semiconductor and systems companies driving development and adoption of emerging DFD methodologies, software tools, and intellectual property offerings.
      http://www.designfordebug.org/

      JTAG Free Resources

      We encourage you to take advantage of the following information on JTAG, available at no charge. View our Technical Leadership Video Access a FREE online Boundary-Scan (JTAG) Tutorial Access the first JTAG Tutorial (145-pages) written by ASSET InterTech when we were still at Texas Instruments. This primer explains the basics of JTAG, the benefits of JTAG testability, JTAG or boundary-scan architecture, some data formats and test flow....
      http://www.asset-intertech.com/products/free_resources.htm

      Pinnacle

      Pinnacle suite provides a high performance, highly scalable design-for-variability implementation solution for the largest Nanometer ICs.
      http://www.mentor.com

      Calibre nmDRC

      The industry standard for design rule checking.
      http://www.mentor.com

      Design-for-test Technical Publications

      Titles include * Embedded Deterministic Test for Low Cost Manufacturing (ITC 2002) * Reducing Simulation Mismatches in Design-for-Test (DFT) Implementation * TestKompress with EDT Technology: Reducing Time and Expense in Test * Embedded Deterministic Test - DFT Technology for Low-Cost IC Manufacturing Test * Using FastScan Diagnostics to Improve Time-to-Volume
      http://www.mentor.com/dft/techpapers/

      International Test Conference

      The world's premier conference dedicated to electronic test technology, covering the complete cycle from design verification, test, diagnosis, failure analysis back to process and design improvement.
      http://www.itctestweek.org/

      DFT Digest.com

      Hi! My name is John Ford, and I write this blog. I have been working in this industry for a little over 23 years (gasp!) in various engineering capacities: test (digital and mixed-signal), DFT, verification, and some design automation. I like doing a variety of things. The bulk of my career has been in Southern California, for companies such as Western Digital, Silicon Systems, and Texas Instruments. Just recently I worked for...
      http://www.dftdigest.com/

      Design of Systems on a Chip: Design and Test

      Second of two volumes addressing the design challenges associated with new generations of the semiconductor technology. The various chapters are the compilations of tutorials presented at workshops in the recent years by prominent authors from all over the world. Technology, productivity and quality are the main aspects under consideration to establish the major requirements for the design and test of upcoming systems on a chip. In...
      http://www.amazon.com

      Calibre nmLVS

      Industry standard physical verification tool for layout versus schematic.
      http://www.mentor.com

      Design for Test.com

      Portal with news and links on the DFT sector.
      http://www.design-for-test.com/

      Explanation: these links are provided as part of our EE glossary project, which seeks to identify the most prominent keywords in embedded systems, embedded software, realtime and rtos, dsp (digital signal processing), system-on-a-chip, microprocessors and microcontrollers, and other constituent elements for embedded systems. While we seek to keep most of the links up-to-date, the user is refered to other primary electronic-based search sites such as: cera2.com, embedded.com, or EDN Magazine. If you have any suggestions of links or definitions, please email!

Mark Twain quote for the day:

The Sphynx is grand in its loneliness; it is imposing in its magnitude; it is impressive in the mystery that hangs over its story. And there is that in the overshadowing majesty of this eternal figure of stone, with its accusing memory of the deeds of all ages, which reveals to one something of what he shall feel when he shall stand at last in the awful presence of God.
- The Innocents Abroad