- ASIC Design For Signal Processing
- ASIC is an acronym for Application Specific Integrated Circuit. It refers to the technology that many chip designers, including Lucent, use for the physical creation of their chips. This project focuses heavily on the creation of such a design, which will be incorporated as part of one of Bell Lab's future research chips.
http://www.geoffknagge.com/fyp/
- Eldo
- High-Performance Circuit Simulator -Verification of A/MS (Analog/Mixed-Signal) circuits and SoC (System on a Chip) designs have reached the limit of classical SPICE simulation techniques. The Eldo simulator is the simulator of choice for IC silicon vendors and Fabless design centers for four reasons: speed, accuracy, convergence, and capacity. When compared to other commercial or internal SPICE simulators, users report a 3X to 10X speed ratio without experiencing a compromise of accuracy, compared to silicon. Eldo provides the best-in-class convergence for all problems. Designers worldwide use Eldo on designs ranging from the lowest complexity of a single cell to systems of up to 300,000 transistors or more.
http://www.mentor.com
- e2v introduces new development and evaluation tool for sensor interface Mixed Signal ASICs
- e2v, the leading designer, developer and manufacturer of specialised components and subsystems, has announced the availability of CAPRI2.0, its innovative new Mixed Signal ASIC Development Kit. CAPRI2.0 is a leading edge toolset for pre-developing and validating entire sensing systems and helping to improve new product time-to-market. e2v's Mixed Signal ASIC (MSA) business unit specialises in providing customised solutions for sensor...
http://www.e2v.com
- ADiT
- ADiT is the tool of choice to address the challenges associated with simulating today’s complex analog and mixed signal circuit designs. It is a fast-SPICE simulation tool that delivers the ability to obtain accurate and reliable simulation results 10X — 100X faster than traditional SPICE tools. ADiT is integrated into the ADVance MS mixed-signal simulation solution and supports both Eldo and HSPICE netlist formats.
http://www.mentor.com
- Parallax
- Microcontroller development tools and small single-board computers that are used by electronic engineers, educational institutions, and hobbyists. Our current product line consists of BASIC Stamp microcontrollers and development software, SX chips and programmer/debuggers, project boards, sensors, educational tools, robotics kits, accessories and the Propeller chip.
http://www.parallax.com
- Aldec Releases Riviera-PRO 2008.06 HDL Simulator. Including New Assertions Waveform Viewer...
- Aldec, Inc., announced the release of Riviera-PRO 2008.06, a behavioral, structural and mixed HDL language simulator for multi-million gate ASIC and FPGA designs. Riviera-PRO 2008.06 includes Verilog® simulation performance enhancements, increased SystemVerilog support, seamless SystemC/C/C++ and HDL co-debugging in common environment and new support for SVA and PSL assertions in the Waveform Viewer. Riviera-PRO supports System Level...
http://www.aldec.com
- Altera Announces Industry’s First 40-nm FPGAs and HardCopy ASICs
- Enabling designers to achieve new levels of integration and innovation, Altera Corporation (NASDAQ: ALTR) today announced the industry’s first 40-nm FPGAs and HardCopy® ASICs. The Stratix® IV FPGAs and HardCopy IV ASICs, both with transceivers options, provide unprecedented densities, performance and low-power leadership. The Stratix IV family has up to 680K logic elements (LEs), 2X bigger than Altera’s Stratix III family, currently the...
http://www.altera.com
- FPGA's vs. ASIC's - What are the Trade Off's (Registration Required)
- Designs that were done in ASICs in the past are done by FPGAs today, faster and for less cost. Complex FPGA design is driving new design approaches. ASIC designs are specialized, offer power and flexibility, and accommodate large designs where FPGA falls short. With so much at stake, where should your company's focus lie? Or is it more of a middle area - a place where structured ASIC can fill the gap?
http://www.iec.org/online/iforums/mentor_graphics/choose.asp
- ChipEstimate.Com - now from Cadence
- ChipEstimate.Com (now owned by Cadence) is an intuitive new tool for IC designers that generates fast and accurate chip estimates. The tool makes it easy for designers to visualize tradeoffs between key design metrics, and across technology nodes and process variants. InCyte lets users generate accurate and optimized chip estimates at the architectural stage of the design process, resulting in significantly shorter design times and lower...
http://www.ChipEstimate.com/
- IEEE International SOC Conference
- Driven by the rapid growth of the Internet, communication technologies, pervasive computing, and wireless and portable consumer electronics, Systems-On-Chip (SOC) has become a dominant issue in today’s ASIC industry. SOCs have created new challenges in Design Methods, Design Tools, Design Automation, Manufacturing, Technology, and Test.
http://www.ieee-socc.org/
Explanation: these links are provided as part of our EE glossary project, which seeks to identify the most prominent keywords in embedded systems, embedded software, realtime and rtos, dsp (digital signal processing), system-on-a-chip, microprocessors and microcontrollers, and other constituent elements for embedded systems. While we seek to keep most of the links up-to-date, the user is refered to other primary electronic-based search sites such as: cera2.com, embedded.com, or EDN Magazine. If you have any suggestions of links or definitions, please email!
embedded asic design